Course Overview
Master chip design, verification methodologies and semiconductor manufacturing for cutting-edge IC development.
About This Course
Comprehensive training in VLSI design and verification covering digital design, RTL coding, synthesis, physical design, and verification using industry-standard EDA tools. Learn SystemVerilog, UVM methodology, and get hands-on experience with real-world projects.
What You’ll Learn
- Digital circuit design and RTL coding
- ASIC/FPGA design flow
- Synthesis and timing analysis
- Physical design and layout
- SystemVerilog and UVM
- Verification methodologies
- Industry EDA tools
- Real chip tape-out process
Course Modules
- Introduction to VLSI & Digital Design
- Verilog/SystemVerilog HDL• RTL Design and Coding
- Synthesis and Optimization
- Static Timing Analysis (STA)
- Physical Design (Place & Route)
- Verification Basics and UVM
- FPGA Design and Implementation
Industry Projects and Tape-out Process
Curriculum
- 1 Section
- 13 Lessons
- 24 Weeks
Expand all sectionsCollapse all sections
- Curriculum13
- 1.1Module 1: Introduction to VLSI & Design Flow
- 1.2Module 2: Digital Electronics Fundamentals
- 1.3Module 3: CMOS Fundamentals
- 1.4Module 4: HDL & RTL Design (VLSI Front-End Design)
- 1.5Module 5: Synthesis & Timing Analysis
- 1.6Module 6: Verification Methodologies
- 1.7Module 7: Physical Design (VLSI Back-End Design)
- 1.8Module 8: Semiconductor Fabrication
- 1.9Module 9: Low Power VLSI Design
- 1.10Module 10: FPGA Design Flow
- 1.11Module 11: Analog & Mixed Signal VLSI
- 1.12Module 12: Industry Practices & Tape-out
- 1.13Module 13: Final Project
